Techniques to Improve Performance Beyond Pipelining: Superpipelining, Superscalar, and VLIW

Preface Superpipelining, Superscalar and VLIW are techniques developed to improve the performance beyond what mere pipelining can offer. Superpipelining improves the performance by decomposing the long latency stages (such as memory access stages) of a pipeline into several shorter stages, thereby possibly increasing the number of instructions running in parallel at each cycle. On the other hand, Superscalar and VLIW approaches improve the performance by issuing multiple instructions per cycle. Superscalar dynamically issues multiple instructions and VLIW statically issues multiple instructions at each cycle. These techniques are pioneers (and now the basis) of modern computer architecture designs. In this chapter, we describe and investigate examples of these techniques and examine how they have affected the designs of modern microprocessors. In general, the performance of a microprocessor is expressed by equation (1): Execution T ime = IC × CP I × clock cycle time (1) In this equation, IC corresponds to the number of instructions in the program at hand, while CPI represents the average number of clock cycles per instruction. clock cycle time represents the duration of a clock cycles. In a basic pipeline architecture, only one instruction can be issued at each cycle (detailed information about pipelined architecture is given in [24, 25, 26]). Overcoming this limitation has been the subject of much work in the past: more specifically, it has been the goal of computer architects to reduce each variable of equation (1). For one thing, CPI can be improved by designing more advanced or